1. Field of the Invention
The field of the invention is data processing, or, more specifically, methods, apparatus, and products for performing an all-to-all exchange on n number of data buffers using XOR swap operations.
2. Description of Related Art
The development of the EDVAC computer system of 1948 is often cited as the beginning of the computer era. Since that time, computer systems have evolved into extremely complicated devices. Today's computers are much more sophisticated than early systems such as the EDVAC. Computer systems typically include a combination of hardware and software components, application programs, operating systems, processors, buses, memory, input/output devices, and so on. As advances in semiconductor processing and computer architecture push the performance of the computer higher and higher, more sophisticated computer software has evolved to take advantage of the higher performance of the hardware, resulting in computer systems today that are much more powerful than just a few years ago.
Parallel computing is an area of computer technology that has experienced advances.
Parallel computing is the simultaneous execution of the same task (split up and specially adapted) on multiple processors in order to obtain results faster. Parallel computing is based on the fact that the process of solving a problem usually can be divided into smaller tasks, which may be carried out simultaneously with some coordination.
Parallel computers execute parallel algorithms. A parallel algorithm can be split up to be executed a piece at a time on many different processing devices, and then put back together again at the end to get a data processing result. Some algorithms are easy to divide up into pieces. Splitting up the job of checking all of the numbers from one to a hundred thousand to see which are primes could be done, for example, by assigning a subset of the numbers to each available processor, and then putting the list of positive results back together. In this specification, the multiple processing devices that execute the individual pieces of a parallel program are referred to as ‘compute nodes.’ A parallel computer is composed of compute nodes and other processing nodes as well, including, for example, input/output (‘I/O’) nodes, and service nodes.
Parallel algorithms are valuable because it is faster to perform some kinds of large computing tasks via a parallel algorithm than it is via a serial (non-parallel) algorithm, because of the way modern processors work. It is far more difficult to construct a computer with a single fast processor than one with many slow processors with the same throughput. There are also certain theoretical limits to the potential speed of serial processors. On the other hand, every parallel algorithm has a serial part and so parallel algorithms have a saturation point. After that point adding more processors does not yield any more throughput but only increases the overhead and cost.
Parallel algorithms are designed also to optimize one more resource the data communications requirements among the nodes of a parallel computer. There are two ways parallel processors communicate, shared memory or message passing. Shared memory processing needs additional locking for the data and imposes the overhead of additional processor and bus cycles and also serializes some portion of the algorithm.
Message passing processing uses high-speed data communications networks and message buffers, but this communication adds transfer overhead on the data communications networks as well as additional memory need for message buffers and latency in the data communications among nodes. Designs of parallel computers use specially designed data communications links so that the communication overhead will be small but it is the parallel algorithm that decides the volume of the traffic.
Many data communications network architectures are used for message passing among nodes in parallel computers. Compute nodes may be organized in a network as a ‘torus’ or ‘mesh,’ for example. Also, compute nodes may be organized in a network as a tree. A torus network connects the nodes in a three-dimensional mesh with wrap around links. Every node is connected to its six neighbors through this torus network, and each node is addressed by its x,y,z coordinate in the mesh. In a tree network, the nodes typically are connected into a binary tree: each node has a parent, and two children (although some nodes may only have zero children or one child, depending on the hardware configuration). In computers that use a torus and a tree network, the two networks typically are implemented independently of one another, with separate routing circuits, separate physical links, and separate message buffers.
While a torus network lends itself to point to point operations, a tree network typically is inefficient in point to point communication. A tree network, however, does provide high bandwidth and low latency for certain collective operations, message passing operations where all compute nodes participate simultaneously, such as, for example, an all-to-all operation. An all-to-all operation is a collective operation on an operational group of compute nodes that sends data from ranked segments of send buffers of all compute nodes into receive buffers in all compute nodes in rank order. The size of each ranked segment of the send buffer may be fixed or vary. Each compute node transmits the contents of each ranked segment of its send buffer only to a correspondingly ranked compute node. The contents of ranked segment 0 go to compute node of rank 0. The contents of ranked segment 1 go to compute node of rank 1, and so on. Each compute node upon receiving the data places it in rank order in a ranked segment of its receive buffer according to the rank of the sending compute node. Data from compute node of rank 0 goes in ranked segment 0. Data from compute node of rank 1 goes in ranked segment 1, and so on. Upon conclusion of an all-to-all operation, each compute node's receive buffer contains in rank order all the data from correspondingly ranked segments of the send buffers of all compute nodes in the operational group. The effect of an all-to-all operation is that all receive buffers in all compute nodes of an operational group contain different data, a matrix inversion of the data sent from the send buffers.
The drawback to current implementations of an all-to-all operation is that such implementations typically involves two sets of buffers—one set of buffers containing the data before the all-to-all operation and another set of buffers for storing the result of the all-to-all operation. Because the size of buffers typically involved in an all-to-all operation is often quite large and the amount of computer memory on each node is limited, utilizing two sets of buffers on the compute nodes consumes valuable memory resources that could otherwise be freed for additional storage needs.